[Barrelfish-users] Bug fix related to FPU context switch on LRPC path for x86_64

[Gerd Zellweger]

Absolutely, with this patch we should also revisit LLVM at some point. I 
remember we had some issues with LLVM code randomly crashing, due to its 
liberal use of SIMD registers. I would suspect this patch is going to 
fix that ;)

Gerd


On 2017-01-18 05:17, Simon Peter wrote:
> Great catch! I don't think I had implemented FPU context switch upon
> LRPC since that was mostly disabled at the time. Andrei's code looks
> fine to me.
> 
> If I were pedantic, I could add that there likely should be a more
> efficient way to context switch the FPU upon LRPC than to replicate
> what's in the dispatch handler (in particular all the branches).
> 
>  -- Simon
> 
> On 01/16/2017 01:36 AM, Timothy Roscoe wrote:
>> 
>> Dear Andrei,
>> 
>> Many thanks - that's great.  Adam: could you have a look at this?
>> 
>> Cheers,
>> 
>>   -- Mothy
>> 
>> At Sat, 14 Jan 2017 14:24:34 +0100, Andrei Poenaru <poenarua at ethz.ch> 
>> wrote:
>>> Dear all,
>>> 
>>> While working on context switching I found a bug regarding the FPU 
>>> context
>>> switching on the LRPC path: no FPU switching is performed on that 
>>> path.
>>> 
>>> When 2 domains (using the FPU) communicate via LRPC the data stored 
>>> in the
>>> registers is not correctly preserved. I was able to derive a test 
>>> starting
>>> from 'lrpc_bench'.
>>> 
>>> In order to fix the issue, I implemented in assembly, on the LRPC 
>>> path, the
>>> same logic as in 'fpu_lazy_top' (function called during a context 
>>> switch on
>>> the normal kernel path).
>>> 
>>> The test and the proposed fix can be found in the attached patch.
>>> 
>>> Best regards,
>>> Andrei
>>> 
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