[Oberon] FPGA Oberon on projectoberon: Verilog instead of VHDL

Jan Verhoeven jan at verhoeven272.nl
Tue Feb 25 15:59:51 CET 2014

Frans-Pieter Vonck wrote
> On Verilog:
> ---------------
> "The designers of Verilog wanted a language with syntax similar to the C
> programming language [..]"
> Anyone has an idea why Wirth choose Verilog instead of VHDL?

I happened to meet Dennis Ritchey lately and he mentioned about this: 
"Wirth is getting older and wiser..."


Jan Verhoeven

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