[Oberon] FPGA Oberon: how is it done...

Frans-Pieter Vonck fp at vonck.nl
Mon Mar 3 15:54:16 CET 2014

Thanks for the link to the PO Computer document.
I will go through the basics of Verilog first.


> FP
>>Still; compare the readabilty of the code of the rs232 driver written in
>>verilog with one written in vhdl
> Please find the description of the RS232 algorithm here (chapter 17.2.5,
> page 20)
> http://www.inf.ethz.ch/personal/wirth/ProjectOberon/PO.Computer.pdf
> Perhaps the Verilog gets more obvious if you read the description (what
> "midtick" does, what "run" is meant for...)
> Jörg

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