[Oberon] Digilent Spartan 3 Board, and ORP and ORG are back
knapjack at gmail.com
Mon Apr 14 22:01:42 CEST 2014
On Mon, Apr 14, 2014 at 9:14 AM, Paul Reed <paulreed at paddedcell.com> wrote:
>> Is that a design problem that would eventually have to be overcome anyway?
> What, that it's not complicated enough? I don't see that as a design
> problem, but many commercial operations would :) Seriously though, I'm
> not sure I understand your question (sorry!).
No apology necessary, I believe it's entirely me.
What I'm pondering is that, say, two years from now, it might be
impossible to source an FPGA board off the shelf that has 1 MB of
SRAM, or perhaps one that has 1 MB of SRAM and all of the other
features that make the Spartan 3 so attractive.
If that is the likely outcome, and it's back either to building your
own board or to porting to something with less than 1 MB of SRAM, what
would you suggest?
>From my basic understanding, it seems like:
a) we're likely headed towards the latter, and
b) the outcome is not pretty
But, if we're really are stuck there anyway, does it make sense to
start designing the "new" least complex memory interface given the new
realities? Or, in other words, if some benefactor had magically paid
you to use the DE0 or DE1 as a requirement from the outset, what would
you have done?
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