[Oberon] Digilent Spartan 3 Board
jan at verhoeven272.nl
Mon Apr 14 22:12:57 CEST 2014
Peter De Wachter wrote:
> [70 ns SRAM] too slow for the current design, isn't it?
It would be too slow for a 30 MHz Z80, but it depends on a lot factors.
It depends on
is there a clock multiplier?
how many clockcycles in one machine cycle?
how many machinecycles for one read- or write-cycle?
If you have a WAIT line, any SRAM timing can be used.
> The CPU runs at 25 MHz = 40ns per cycle.
Per clock cycle. Not machine cycle.
I'm not an FPGA expert so I don't know how the clock frequency
translates to the timing results of the constructed output pins.
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