[Oberon] RISC5

eas lab lab.eas at gmail.com
Wed Apr 16 09:30:12 CEST 2014

Let me admit, that I have lost understanding of the overall structure
of how the V5 project is developing.

So here's my attempted framework, which can be corrected, so that
we all understand the structure.

[CB once agreed with me that the manual should never be written by
the developer, but rather by an ignorant outsider].

A minimalist, custom CPU was designed, to implement 'Oberon'.
Apart from the ALU, it would also need I/O & memory.

Such hardware can be built in FPGA, ASICs, ...etc. Call it V5.
It seems that the intended hardware became unavailable?
But since substantial new software was designed, eg. the
code-generation specifically for V5, part of the compiler; there
must have been some 'real-live' V5 hardware, to test the code?

Or was the hardware simulated at that stage already?
No; because a new/different emulator would not have been
Going back to the P-code interpreters [which substantial
experience of, 'biases' my outlook] It's easy the parse,
code-generate & run eg.
     Out.Int(MinimalOf(Aglobal, BlocalVar)+Aglobal,4)

But how do you manufacture the TextFrame and Out.Int
into it?
Recursive descent compiling and making FrameBuffers
hardly fit into the same 'book'.

Apparently the FrameBuffer creation, for the rPi project,
is handled by SDL?
Is this project getting out of control and potentially destroyed,
eg. by spurious complexity: floating point technology ....?

Who's going to write a clear/Wirthian explanation of how all
the stages fit together?
Or is that suitable for a wiki?

== Chris Glur.

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