[Oberon] RISC5

eas lab lab.eas at gmail.com
Thu Apr 17 12:58:14 CEST 2014

joerg.straube wrote:-
]Depends on the definition of "emulated" vs "implemented" :-)
]Couldn't you do the following analogy?
] Verliog code  = PdWs emulator code
] Verilog tools = C compiler
] Spartan 3     = host environment

Yes, that's how I see it too:
 the Verliog code is 'compiled' by Verilog tools into the
<physical configuration> of the silicon, resulting in the
register-set & buss/s which implement the [partial] V5 system.

The hidden/mysterious part for me is the display/textFrames.
Does V5 drive standard VGA?
Where's the code showing;
  VGA -> FrameBuffer -> ETHOviewer.

When I built 8 bit P-code interpreters, [wire wrapped! I've still
got a 68?3xx one which I failed to get working], I just output
a stream of bytes to the mechanical TTY.

And the CPM-based version used the BIOS-like <outChar(char)> function,
IIRC ? But that was just a toy compared to V5 with TextFrames.

==Chris Glur.

More information about the Oberon mailing list