[Oberon] Spartan 6 Kickstarter project

Jörg joerg.straube at iaeth.ch
Mon Jun 23 16:08:58 CEST 2014


Okay, I looked at the pictures of the board.
Most probably there is no space for 4 chips in parallel :-(


-----Original Message-----
From: Jörg [mailto:joerg.straube at iaeth.ch] 
Sent: Montag, 23. Juni 2014 15:44
To: paulreed at paddedcell.com; 'ETH Oberon and related systems'
Subject: Re: [Oberon] Spartan 6 Kickstarter project

Hi Paul

Today's RISC5Top Verilog source splits the 20 bits address bus to
two SRAM chips with 18 bits address and 16 bit output.
                                +-! 256K !-- 16 bit
                                ! +------+
adr (20bit) --- SRadr (18bit) --+ 
                                ! +------+
                                +-! 256K !-- 16 bit

As the Papilio DUO page only points to ONE SRAM datasheet (IS61WV5128)
but offers TWO versions of the board (512K and 2M) I could imagine that
the 2M version has 4 of those chips in parallel.

If this is the case, today's "RISC5Top" Verilog could be re-written to
                                +-! 512K !-- 8 bit
                                ! +------+
                                ! +------+
                                +-! 512K !-- 8 bit
adr (20 bit) --- SRadr (18bit) -! +------+
                                ! +------+
                                +-! 512K !-- 8 bit
                                ! +------+
                                ! +------+
                                +-! 512K !-- 8 bit

The upper half of those SRAM chips would not be used...


-----Original Message-----
From: Paul Reed [mailto:paulreed at paddedcell.com] 
Sent: Montag, 23. Juni 2014 13:45
To: ETH Oberon and related systems
Subject: Re: [Oberon] Spartan 6 Kickstarter project

Hi Ulrich, (bcc others)

> the Papilo DUO kickstarter project [1] (4 days to go) has 2MB SRAM (not
> SDRAM) on board of its PAPILIO DUO DELUXE.
> With the Classic Computing Shield you also get VGA output, 2 x PS/2 and
a micro SD socket.
> Looks to me, that's what you need for RISC-Project-Oberon, right?


Looks perfect, but the devil is in the detail, as always.  I think their
SRAM is x8, so even though it's a good speed (10nS), the board seems to be
designed for retro 8-bit processors not 32-bit RISC.  The Digilent
Spartan-3 board has two x16 10nS SRAMs set up in parallel, which is why
it's so neat.

However, maybe things are changing - it's refreshing that the Papilio
project description says: "SRAM - Easy to use SRAM is a must. We've used
SDRAM in the past and it was a big mistake! The strict timing requirements
and interfacing caused fits for everyone. SRAM is asynchronous and dead
easy to use, you will greatly appreciate the simplicity of SRAM in your

People privately email me questions along the lines of: "would it be
possible to port the RISC Oberon system to FPGA board X".  I'm BCC'ing
some in, and suggest they perhaps follow the Oberon mailing list instead
to understand why it's currently a very difficult question to answer. 
Whilst I would be absolutely delighted to see something viable, "possible"
is not the same as "easy" or even "sensible".

The point of Project Oberon is not just to make something work, starting
from scratch, but to make it completely clear and understandable (and
convincing).  The entire book is just that, and amply rewards a careful
read.  I think it's only after you read the whole book through that you
can really start claiming to understand the philosophy.

F V Tkachov (2014 J. Phys.: Conf. Ser. 523 012011) recently perhaps put it
even more starkly than Prof. Wirth: the natural tendency towards
unnecessary complexity creates vulnerability (The Kalashnikov Principle),
and should be avoided.

Paul Reed

Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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