[Oberon] Macros or Inlining in Project Oberon 2013
greim at schleibinger.com
Sun Jul 6 17:48:55 CEST 2014
the only reason for macros or inlining is, to boost performance for very
time critical things (see the car example as cited above).
But we should keep in mind that Project-(FPGA)-Oberon is not only a
compiler and OS but also a reconfigurable hardware.
So realizing time or mission critical things in an own hardware unit is
the fantastic thing that is (more or less) unique with Project-FPGA-Oberon.
The only drawback is, that there is no HDL which is so clear and
straight then Oberon is (not even Chisel on top of Scala on top of Java,
or MyHDL on top of Python).
I don't know if Active Cells development at the ETHZ
or the Avalanche project
will work on this task.
Anybody out there from the ETH?
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