[Oberon] FPGA - SRAM vs. BRAM

[Walter Gallegos]

Note also that to target on Altera chips or other any than Xilinx you need 
translate the clock management from Xilinx to the target family.

-----Mensaje original----- 
From: nyaaa at nyaaa.de
Sent: Thursday, June 25, 2015 7:13 AM
To: oberon at lists.inf.ethz.ch
Subject: Re: [Oberon] FPGA - SRAM vs. BRAM

There has been talk on Parallax Inc.'s discussion forum [1], that
version 15.0 of Altera's gratis Quartus II web edition design software
now also supports the 5CEFA9F23C8N FPGA as used on the BeMicro CV A9
development board (although the Quartus II web site still said otherwise
last time I checked), which appears to be sold by Arrow Electronics for
$149 [2]. This particular FPGA appears to feature 12Mbit of M10K on-chip
memory, on which a quick search engine query only found me some glossary
entry [3].

I wonder, if this on-chip memory could easily be configured to behave
like the SRAM that's currently used on the older board without
complicating the code. Has anybody used Altera's FPGAs in the past and
can comment on their devices or software?

[1]
http://forums.parallax.com/showthread.php/160968-Quartus-II-version-15.0?p=1333217&viewfull=1#post1333217
[2]
https://parts.arrow.com/item/detail/arrow-development-tools/bemicrocva9
[3]
http://quartushelp.altera.com/current/mergedProjects/reference/glossary/def_m10k.htm



--
Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
https://lists.inf.ethz.ch/mailman/listinfo/oberon