[Oberon] Oberon Digest, Vol 135, Issue 14

[Magnus Karlsson]

Interesting.

One concern I have here is the complete lack of revision control for the 
RISC5 Verilog source files.  When I started to play with Oberon for 
Pipistrello I grabbed the Verilog source files from 
http://www.projectoberon.com in a file called RISC5Verilog.zip, where 
all included files were dated Feb 15, 2014.  Later someone brought to my 
attention that I wasn't using "the latest version" and sure enough the 
file RISC5Verilog.zip was now different - three files now had a time 
stamp of March 3, 2015 (RISC5Top.v, RISC5.v and RISC5.ucf) - without any 
indication on the web site that the zip file had been updated.  A quick 
diff showed that a GPIO port had been added (which was not a big concern 
for me) as well as changes to the core RISC5 processor with no 
documentation or even a comment at all regarding the reason for the 
changes (big concern for me, bug fixes or added functionallity?).

I think a bare minimum here is to include a date in the name of the zip 
file (e.g. call it RISC5Verilop_ 20150303.zip) so that it's clear to all 
what version they look at.  I think it's also bare minimum to have a 
short revision history at the top of each source file that dates the 
change and gives a reason for the change.

Cheers,
Magnus


On 8/26/2015 6:49 AM, Paul Reed wrote:
> Hi David,
>
>> Just to 'chime in' with what Wojtek is saying.    If you look at the
>> Verilog code, there is a GPIO In and GPIO out port.   Those are not
>> mentioned in Ch. 17 that is available on the Project Oberon page.
> That's the exception which proves the rule.  Prof. Wirth added a couple of
> IOs while he was experimenting with programming PIC chips for a project
> (see his section on PICL), and I persuaded him to make it an 8-bit GPIO
> port.  So my bad!  :)  Consider it experimental.  All the rest is
> documented, right?
>
> Cheers,
> Paul
>
>
>
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