[Oberon] RISC5 implementation issues.

[skulski at pas.rochester.edu]

Magnus wrote:

> OK, so I decided to try to implement the clocking as Walter suggested

Ou of curiosity: Chapter 10 of the book "FPGA prototyping.." by Pong. P.
Chu is devoted to SRAM interfacing. He is using the same Spartan-3 board
that Paul Reed used. All the timing issues are thoroughly analyzed. Three
different designs are presented and discussed. The book has two versions:
VHDL or Verilog (two separate books). So I am curious why this discussion
is not referencing the textbook but rather it is starting from scratch?

Wojtek