[Oberon] FPGA - Bitmap Replace Horizontal Line
Jörg
joerg.straube at iaeth.ch
Tue May 23 15:15:01 CEST 2017
Chris
Okay. Thanx for the update.
br
Jörg
-----Original Message-----
From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of Chris Burrows
Sent: Dienstag, 23. Mai 2017 15:12
To: 'ETH Oberon and related systems' <oberon at lists.inf.ethz.ch>
Subject: Re: [Oberon] FPGA - Bitmap Replace Horizontal Line
Hi Joerg,
Not that boards that support RISC5 Project Oberon and are equipped with 2MB of 10ns SRAM do already exist. E.g. Saanlima Electronics Pipistrello + 2MB Oberon wing and the Pepino LX25 with 2MB RAM.
http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello
http://www.saanlima.com/pepino/index.php?title=Welcome_to_Pepino
However, as far as I know, only the 1MB version of Project Oberon is distributed with them. I haven't been able to track it down yet but I'm convinced I have had an experimental 2MB-enabled version of Project Oberon working on the Pepino.
There is also an Oberon RISC5 for Pepino which has the video system modified to 3-bit RGB (each pixel takes up 4 bits in video memory):
https://github.com/Saanlima/Pepino/tree/master/Projects/RISC5Verilog_Pepino_RGB
Regards,
Chris Burrows
CFB Software
http://www.astrobe.com/RISC5
> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> Jörg
> Sent: Tuesday, 23 May 2017 1:48 AM
> To: 'Tomas Kral'; oberon at lists.inf.ethz.ch
> Subject: Re: [Oberon] FPGA - Bitmap Replace Horizontal Line
>
> Tomas
>
> Today, the RISC5 CPU runs in an environment with only 1MB of memory.
> This 1MB must hold all code, data (heap and stack) and screen.
>
> Here the amount of memory the screen takes up:
> - XGA, 2 colors = 9% (<-- today)
> - SVGA, 4 colors = 11%
> - XGA+, 2 colors = 12%
> - WXGA, 2 colors = 12%
> - SVGA, 8 colors = 17%
> - XGA, 4 colors = 19%
>
> I would say for more colors and/or higher resolution you would need a
> board with more memory.
>
> br
> J rg
>
> -----Original Message-----
> From: Tomas Kral [mailto:thomas.kral at email.cz]
> Sent: Montag, 22. Mai 2017 12:07
> To: oberon at lists.inf.ethz.ch
> Cc: joerg.straube at iaeth.ch
> Subject: Re: [Oberon] FPGA - Bitmap Replace Horizontal Line
>
> Hi Joerg,
>
> EDIT(1) - comment changes
>
> I am digesting your post, while looking into `Display.Mod'.
>
> I believe the colour may be encoded into bitmap itself, the below is
> unrolled loop of `ReplaceHLine'. I hope I am not being too silly
> here, but it does things for me with x,w pixel granularity.
>
>
> PROCEDURE ReplaceHLine(x, src, dst, w: INTEGER);
> VAR bt: BYTE; w0, wd: INTEGER; pix: SET;
> BEGIN
>
> (* (pix * {maskleft*8..31} * {0..maskright*8-1}) *)
>
> w0 := w MOD 32;
> WHILE w > 0 DO
>
> (* begin - clear line white *)
> (* begin - paint black line *)
> DEC(w, 32); wd := -1;
> IF w < 0 THEN wd := SYSTEM.VAL(INTEGER, SYSTEM.VAL(SET,
> wd)*{0..w0}) END;
> SYSTEM.GET(dst, pix);
> SYSTEM.PUT(dst, SYSTEM.VAL(SET, LSL(wd, x MOD 32)) + pix);
>
> IF (x MOD 32 > 0) & (w > 0) THEN
> SYSTEM.GET(dst+4, pix);
> SYSTEM.PUT(dst+4, SYSTEM.VAL(SET, -1)*{0..x MOD 32-1} + pix)
> END;
> (* end - paint black line *)
>
> (* begin - invert black line *)
> wd := -1;
> IF w < 0 THEN wd := SYSTEM.VAL(INTEGER, SYSTEM.VAL(SET,
> wd)*{0..w0}) END;
>
> SYSTEM.GET(dst, pix);
> SYSTEM.PUT(dst, SYSTEM.VAL(SET, LSL(wd, x MOD 32)) / pix);
>
> IF (x MOD 32 > 0) & (w > 0) THEN
> SYSTEM.GET(dst+4, pix);
> SYSTEM.PUT(dst+4, SYSTEM.VAL(SET, -1)*{0..x MOD 32-1} / pix)
> END;
> (* end - invert black line *)
> (* end - clear line white *)
>
> (* begin - PaintHLine proc *)
> SYSTEM.GET(src, wd); INC(src, 4);
> IF w < 0 THEN wd := SYSTEM.VAL(INTEGER, SYSTEM.VAL(SET,
> wd)*{0..w0}) END;
>
> SYSTEM.GET(dst, pix);
> SYSTEM.PUT(dst, SYSTEM.VAL(SET, LSL(wd, x MOD 32)) + pix);
>
> INC(dst, 4);
> IF x MOD 32 > 0 THEN
> SYSTEM.GET(dst, pix); wd := ASR(wd, -(x MOD 32));
> SYSTEM.PUT(dst, SYSTEM.VAL(SET, wd)*{0..x MOD 32-1} + pix)
> END
> (* end - PaintHLine proc *)
>
> END
> END ReplaceHLine;
>
> I wish to support 16 coulours in future (after necessary vid.v
> changes), that is my life long challenge next to Verilog
> comprehension.
>
> Tomas
>
> On Mon, 22 May 2017 11:14:05 +0200
> J rg <joerg.straube at iaeth.ch> wrote:
>
> > Hi Tomas
> >
> > These are the definitions Oberon uses
> > 0 = background = black
> > 1 = foreground = white
> >
> > Paint = src AND pat (1 in pattern is interpreted as "white")
> > Invert = src XOR pat
> > Replace = draw pattern with "col"
> > black: src AND ~pat
> > white: src AND pat (= paint)
> >
> > br
> > J rg
> > -----Original Message-----
> > From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> > Tomas Kral
> > Sent: Montag, 22. Mai 2017 10:34
> > To: Oberon@ <lists.inf.ethz.ch.Oberon at lists.inf.ethz.ch>
> > Subject: [Oberon] FPGA - Bitmap Replace Horizontal Line
> >
> > Hi,
> >
> > I was scratching my head over how to implement the `replace'
> > mode. Seems more complicated than `invert' mode, which only applies
> > `/' set operator in place of `+' in the PaintHLine.Mod (see earlier
> > post)
> >
> > I thought to erase destination rectangle with $0000$ first than
> paint
> > bitmap in the cleared area.
> >
> > To erase destination rectangle, appears to be done in two steps,
> paint
> > black rectangle, then invert it.
> >
> > The replace mode can be done in three steps:
> > [a] paint black rectangle
> > [b] invert black rectangle
> > [c] paint bitmap in the cleared area
> >
> > The above replace mode performs 3 times worse to Paint/Invert
> modes.
> >
> > What do you think?
> >
>
>
>
> --
> Tomas Kral <thomas.kral at email.cz>
>
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related
> systems https://lists.inf.ethz.ch/mailman/listinfo/oberon
--
Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
https://lists.inf.ethz.ch/mailman/listinfo/oberon
More information about the Oberon
mailing list