[Oberon] RISC-5 and memory

Jörg joerg.straube at iaeth.ch
Wed Oct 4 23:25:55 CEST 2017


some remarks on memory.

> On the other hand, the one megabyte FPGA card just happened to be available. It is not the only possible solution even in the FPGA world. Let me compare memory prices to make it clear. Two 0.5 MB chips type IS61LV25616AL-10TL comprising the 1 megabyte cost $9.26 at DigiKey. A single 512 megabyte chip type AS4C256M16D3LB-12BCN costs $10.59. So we are looking at the cost effectiveness differing by orders of magnitude. 
> These are different technologies. One is simple to use, while the other is much harder. On the other hand, boards using the latter have been built. (For example, Arty from Digilent.) It is not that clear to me that the language definition and compiler technology should stay at the level of asynchronous SRAM rather than advance into the era of DDR3L.

First let me start with the statement: I’m not the HW guru. So, I can be completely wrong.
I took your arguments and started to investigate on the reasons why NW decided for SRAM instead of the much larger and cheaper SDRAM.

The key thing in ProjectOberon is not the language or the compiler, the key topic is his own CPU, the "RISC-5“.
As with the Oberon language, the Oberon OS and the Oberon compiler, NW seems to follow the same principle for the Oberon CPU: make it simple but not simpler.

I studied the RISC-5 Verilog code and googled a bit because I was wondering how today’s CPU tackle the fact that SDRAM is MUCH slower than SRAM. I found that today's CPUs implement several optimization techniques, e.g. pipelining. But I think the fundamental point to overcome the low speed of SDRAM is that today’s architecture use caches. Either only L1 or a combo of L1 and L2 cache before they access slow SDRAM.

To keep the CPU design simple, the RISC-5 does not implement neither a pipeline nor does it use a two stage cache approach to access RAM.
I come to the conclusion that the whole SRAM in ProjectOberon can be seen as one big cache in today’s CPUs wording.

Or in other words: We would have to add a cache strategy to RISC-5 environment to use SDRAM.
When we did that, I have no clue whether we would then be forced to introduce special video RAM as well.

I’d like to get feedback.


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