[Oberon] RISC-5 and memory

[Magnus Karlsson]

On 10/6/2017 10:53 AM, Skulski, Wojciech wrote:
> From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of peter at easthope.ca [peter at easthope.ca]
>
>> How many MiB would you want?
> Enough for V4, S3, and Component Pascal running natively on RISC5. I would guess 16 MB should be enough, but more is better.
>
FYI, RISC5 CPU only supports up the 24-bit addresses, i.e. the 
architecture is limited to 16 MB address space.  Part of this memory 
space is used for I/O and boot-loader ROM.
It used to be that RISC5 only supported 20-bit addresses but NW extended 
the address range to 24 bits in the 25.9.2015 version.

Magnus