[Oberon] FPGA - Boot over serial line

Chris Burrows chris at cfbsoftware.com
Tue Oct 10 14:48:14 CEST 2017

> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> Tomas Kral
> Sent: Tuesday, 10 October 2017 10:59 PM
> To: Oberon@
> Subject: [Oberon] FPGA - Boot over serial line
> Hi,
> After re-reading chapter 14.1. of PO2013 plus Andreas's git repo
> `building-tools', I wish to do an exercise of initial system boot
> over serial line.
> My understanding is that asterisked `BootLoad' module is placed in
> `prom.mem', wherefrom it is fetched by FPGA logic with Verilog module
> PROM, on power-cycle or reset.

See Paul Reed's message in this mailing list:

'Boot procedure FPGA Oberon' (23 Jan 2014)


Chris Burrows
CFB Software

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