[Oberon] FPGA - nRF24L01 `RPI Net' server

Tomas Kral thomas.kral at email.cz
Wed May 2 21:26:28 CEST 2018


Looking into `PI' low level `SPI' code, chip is controlled by `CE' and
`CSN' pins. Reading `SCC.Mod' and `SPI.v' code I do not see these
signals used, possible?

Many thanks.

Tomas Kral <thomas.kral at email.cz>

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