[Oberon] FPGA - nRF24L01 `RPI Net' server
thomas.kral at email.cz
Thu May 3 10:56:27 CEST 2018
On Wed, 2 May 2018 20:36:19 +0100
Paul Reed <paulreed at paddedcell.com> wrote:
> They are SPI control register bits 3 and 1 respectively; see SCC.Mod,
> bits netEnable and netSelect, respectively. netSelect is inverted by
> the hardware, so writing a 1 to the control port activates the signal
> (sends it low) - this does not apply to netEnable.
Thank you. What is the function of `spiFast'?
I read in the library code that `NRF' supports slow byte mode, and fast
Tomas Kral <thomas.kral at email.cz>
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