[Oberon] FPGA - nRF24L01 `RPI Net' server

Jörg joerg.straube at iaeth.ch
Fri May 4 17:49:21 CEST 2018


The approach to rely on time constants in loops is not the best one...
The chip is able to tell you when it received a packet and it can tell you
when it sent the packet.
It does so by setting bits in registers. Please have a look at the register
map and find those bits.
When the chip told you that there happened something, treat the packet
accordingly (get the packet off the chip or prepare a new one to send) and
(important!) tell the chip that you're done by resetting the bits mentioned


-----Original Message-----
From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of Tomas
Sent: Friday, May 04, 2018 5:26 PM
To: Oberon at lists.inf.ethz.ch
Subject: [Oberon] FPGA - nRF24L01 `RPI Net' server


I have made some progress. I am able to transmit packets of
multiple payloads. The trick seems in adjusting time loop constants in
various places, plus delays and retries. The setting slightly differs
between `PI' and `Oberon', having no exact explanation, except that each
platform runs at different speed. This may brake compatibility
though with other `Oberon' station nodes, as I have only one `FPGA'
board and one `PI' this may not be an issue.

4.7uF decoupling caps removed for now.

I can try to add other functionality to `Net.cpp' server, as I hope for
being able to transfer files in the end when proved possible.

Tomas Kral <thomas.kral at email.cz>
Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems

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