[Oberon] Load/Store instruction and Status register
sinu.nayak2001 at gmail.com
Fri May 11 15:33:38 CEST 2018
1.a small doubt on PO 2013 risc architecture.
2. a small doubt on working of PO 2013 OS.
Here are the doubts.
1. In ORG Module I see
PROCEDURE DeRef*(VAR x: Item);
ELSIF x.mode = RegI THEN Put2(Ldr, x.r, x.r, x.a); NilCheck
BEGIN IF check THEN Trap(EQ, 4) END
PROCEDURE Trap(cond, num: LONGINT);
BEGIN Put3(BLR, cond, ORS.Pos()*100H + num*10H + MT)
We see, here two instructions are being generated consecutively.
Put2(Ldr, x.r, x.r, x.a); //here x.r becomes Mem[x.r + x.a]
Put3(BLR, EQ, ORS.Pos()*100H + 4*10H + MT); //this is for NilCheck
To my understanding, here our interest is to do the
NIL check for the pointer/address being dereferenced.
Here pointer/address is given by x.r + x.a.
We need to check if this is 0 or not.
So here, will the status register(N,Z,C,V) gets set by
i. x.r + x.a address calculation operation or
ii. for the received value in x.r?
In PO.Computer.pdf I read:
Whenever a register is written, the condition flags *are also* affected.
They are N (aluRes negative), Z (aluRes zero), C (carry), and OV (overflow).
The latter apply only to addition and subtraction.
If I understood this correctly, it means
status register(N,Z,C,V) gets set for the received value in x.r.
That means we didn't check the address to be 0,
but rather we checked if the value received is 0.
Looks like I am missing something.
Not able clarify my dilemma from RISC-Arch.pdf and PO.Computer.pdf.
Kindly guide me where I can find
how Load/Store instructions affect Status register(N,Z,C,V).
2. In Put3(BLR, EQ, ORS.Pos()*100H + 4*10H + MT) instruction,
we embedded source code position and trap number(4)
in to the branch instruction itself.
Where and When this instruction will be decomposed
to get position information and trap number?
With thanks and best regards,
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