[Oberon] FPGA - System Crash

Hellwig Geisse hellwig.geisse at mni.thm.de
Sat May 12 13:47:21 CEST 2018

On Sa, 2018-05-12 at 12:40 +0200, Andreas Pirklbauer wrote:

> Ok. Will do so from now on for the various tools and also for Experimental Oberon.

Thanks a lot.

> Is THM-Oberon, i.e. the port of Oberon system to Terasic's DE2-155 FPGA
> development board for educational purposes?

Ah, you found my little project... :-)

No, not yet. It's just a hobby for me too. I owned the books describing
the system since when they came out, but never did anything serious
with them. A few months ago I accidentally learned about the 2013
relaunch, and that Oberon is now running on its own soft-core processor.
This sparked my interest again, and I decided to take a closer look.

The port to Terasic's DE2-115 board isn't completed yet. The hardest
part was substituting the static RAM used in the original (but that
was to be expected). Fortunately, the DE2-115 also has a static RAM
on board, but with a different organization (x16 instead of x32), so
there are wait states involved. In the long run, I intend to use SDRAM
with appropriate caches, as was discussed on this list not long ago.

On Sa, 2018-05-12 at 16:03 +0530, Srinivas Nayak wrote:

> Glad to know that you are also working on a C version of ORC.Mod.
> Can I see your code at Github?

The code resides on our on-campus GitLab installation for now. If
there is interest, I will happily transfer it to GitHub.


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