[Oberon] FPGA - nRF24L01 `RPI Net' server

eas lab lab.eas at gmail.com
Wed May 16 03:05:31 CEST 2018

>> The trick seems in adjusting time loop constants in
>> various places, plus delays and retries. The setting slightly differs
>> between `PI' and `Oberon', having no exact explanation, except that each
>> platform runs at different speed..

> The approach to rely on time constants in loops is not the best one...

Yes, AFAIK the now mature/well-established protocol is:
  interrupt-driven switching;
 but there must be some timeout to handle abnormal/bad delays?

> The chip is able to tell you when it received a packet and it can tell you
> when it sent the packet.

It tells THAT it has received a packet and it knows/records THAT it
sent a packet.
I expect the TxSentBit is set AFTER the last bit-of-the-packet has been sent.

> It does so by setting bits in registers. Please have a look at the register
> map and find those bits.

> When the chip told you that there happened something, treat the packet
> accordingly (get the packet off the chip or prepare a new one to send) and
> (important!) tell the chip that you're done by resetting the bits mentioned
> above.

IF NewRx THEN HandleRX&ResetBit;
IF TxDone THEN andleTX&ResetBit;

There's no "real time catch the ball".
The protocol caters for communication between very different speed nodes.


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