[Oberon] Oberon board availability

Jörg joerg.straube at iaeth.ch
Tue Jul 31 18:50:30 CEST 2018


> We have just finished preparing a new disk image and Verilog bitstream
files specifically to run the Project Oberon Workstation on the Pepino LX9
FPGA development board 'out-of-the-box'. 

Great. Will try to update the Verilog files for "my" Pipistrello (LX45) as

> This release is based on the very latest Oberon sources (July 2018) and
Verilog sources (Jun 2018) as described in 'An Update of the RISC5
Implementation', by Niklaus Wirth 15.6.2018:
> https://people.inf.ethz.ch/wirth/ProjectOberon/RISC5.Update.pdf

That NW changed the internals of the processor implementation is one thing,
adding additional new CPU instructions for interrupts (and new Oberon syntax
to the compiler) is another...
In my point of view, it's a new processor supporting interrupts. Good, it's
backward compatible to previous RISC-5 but new.
Of course it's questionable whether this interrupt add-on is worth a new
major number like RISC-6 but perhaps RISC-5a or RISC-5.2 or so.
Perhaps not widely known, but in Oberon you can ask the RISC5 processor to
reveal its version. But not even this internal versioning was incremented in
the Verilog code.
So, I have no chance to find out in SW whether the underlying CPU is
"previous RISC5" or "new RISC5 supporting interrupts".
>From compatibility point of view (and general versioning point of view) the
add-on's implementation is not optimal...

I would have incremented the internal CPU version to e.g. h'52 like so:
            (~u ? C0 : (~v ? H : {N, Z, C, OV, 20'b0, 8'h52}))) :


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