[Oberon] Oberon board availability
chris at cfbsoftware.com
Wed Aug 1 10:37:12 CEST 2018
> -----Original Message-----
> From: Jörg [mailto:joerg.straube at iaeth.ch]
> Sent: Wednesday, 1 August 2018 2:21 AM
> To: chris at cfbsoftware.com; 'ETH Oberon and related systems'
> Subject: RE: [Oberon] Oberon board availability
> > This release is based on the very latest Oberon sources (July 2018)
> > and
> Verilog sources (Jun 2018) as described in 'An Update of the RISC5
> Implementation', by Niklaus Wirth 15.6.2018:
> > https://people.inf.ethz.ch/wirth/ProjectOberon/RISC5.Update.pdf
> That NW changed the internals of the processor implementation is one
> thing, adding additional new CPU instructions for interrupts (and new
> Oberon syntax to the compiler) is another...
There aren't any additional CPU instructions. Interrupts are actually
defined in an earlier stage (RISC3) of Wirth's RISC Architecture
specification. Refer to 'The Design of a RISC Architecture and its
implementation with an FPGA':
Similarly they have always been in the Project Oberon compiler - well at
least since Nov 2013 which is the earliest version of ORG.Mod I could get my
hands on quickly. However, I don't think they had actually been implemented
in the Project Oberon FPGA hardware until the recent change.
Interrupt procedures are an extension to the language so you should not
expect to see any reference to them in the Oberon Language Report. They
would not be relevant to many implementations and should not be considered
to be portable.
As for naming issues, be aware that the recent set of changes includes a new
'RISC5a' package which is RISC5 without floating point support. I had been
thinking of referring to my CASE-related indexed branch instruction
extension RISC5a so I'm glad I didn't ;-)
More information about the Oberon