[Oberon] FPGA - Display.Mod 4-bit colour

Tomas Kral thomas.kral at email.cz
Thu Oct 18 11:29:42 CEST 2018

On Tue, 16 Oct 2018 14:57:11 +0200
Tomas Kral <thomas.kral at email.cz> wrote:

> I cannot decide on the
> palette map. In RGB triplet, leftmost byte influences RED most,
> middle green, and last blue.

Quite the opposite.

Best results obtained so far, by reordering bits in RGB register.
// RGB[7:0] = BB GGG RRR
assign RGB = {color[23:22], color[15:13], color[7:5]};

Which I believe is matching resolution of Pepino LX9 board.

Colour map now appears like this.

 00000000  black
 00000080  dark red | 00FFFFFF  white - based on SW[6]
 00008000  green
 00008080  yellow
 00800000  deep blue
 00800080  magenta
 00808000  cyan
 00808080  grey
 00C0C0C0  light grey
 000000FF  red
 0000FF00  light green
 0000FFFF  light yellow
 00FF0000  blue
 00FF00FF  light violet
 00FFFF00  light cyan
 00FFFFFF  white

In invert mode SW[7], the colours do not swap as opposite, which makes
me wonder of bit reversal.

// RGB[7:0] = RRR GGG BB 
assign RGB = {<<{color[7:5]}, <<{color[15:13]}, <<{color[23:22]}};

I googled that `<<' stands in Verilog for stream operator doing bit
reversing, if I am not mistaken and the above stands to be corrected.
It could also be little endianness that I often confuse.  

I really need to read some book on Verilog and FPGA, I have PDF by
Pong, if that is good one.

Tomas Kral <thomas.kral at email.cz>

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