[Oberon] RiskFive update

Skulski, Wojciech skulski at pas.rochester.edu
Thu Oct 18 21:43:37 CEST 2018

Another small step. We can talk to the Artix35T over JTAG, using Digilent HS2 Rev. A and Vivado 2014.2. The screen shot is now posted to the News section of the website www.RiskFive.com. The FPGA is not programmed yet, but we can measure the internal core voltage and the chip temperature over time, reading the on-chip ADC. 

ISE 14.7 is not capable of seeing Artix35T, because only two largest Artix chips are supported under ISE. I tried ISE 14.7 and the JTAG communication did not work. One has to use Vivado with Artix35T. As you can see, it works. So we are on our way to use these boards for development.

Thank you -- Wojtek
From: Skulski, Wojciech
Sent: Sunday, October 14, 2018 12:32 AM
To: ETH Oberon and related systems
Subject: RiskFive update


I posted photographs of the RiskFive boards to RiskFive.com. The boards arrived a few days ago. A photo of a powered system is posted on the News page.

Waiting for these boards during last two months we (i.e., interns working on the project) developed Wiznet W5500 communication over Ethernet, using MicroBlaze and C. It was a part of the original plan posted on the "Work plan" page. The interns used Arty-7 and an Arduino W5500 wing for this work. The Oberon part of this project got delayed due to incomplete understanding of the RISC5 Verilog.

As soon as the Arty part is finished, we will post a report and move on the new RiskFive boards.

Thank you,

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