[Oberon] Updated RISC5 firmware

Skulski, Wojciech skulski at pas.rochester.edu
Thu Oct 25 18:05:19 CEST 2018


An "Update of the RISC5 Implementation" by Niklaus Wirth, 15.6.2018 starts with 

   module RISC6(input clk, rst, irq, stallX,

Apparently there were some plans to reshuffle the organization of the firmware. But then the file Risc5a.v uses the old name RISC5.

From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Walter Gallegos [waltergallegos at vera.com.uy]
Sent: Thursday, October 25, 2018 7:18 AM
To: ETH Oberon and related systems
Subject: Re: [Oberon] Updated RISC5 firmware

Apparently, some new versions of RISC5 are converging into my vision of
a soft processor for FPGA. RiscCore: no floating point, does not use DSP
blocks, has interrupts, data bus and code bus.

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