[Oberon] Oberon 2 compiler for RISC5

Skulski, Wojciech skulski at pas.rochester.edu
Thu Nov 8 04:53:51 CET 2018


both simple and OP2 compiler would be great to have. The RISC5 back end for the OP2 for cross compilation, and the native Oberon-2 compiler for small embedded systems. At least I can see value in the full fledged FPGA-based Oberon System. I hope that Linz V4 can be hosted in four megabytes offered by RiskFive. A scaled down version can probably be hosted by the 1 meg board. In a longer run a full System 3 can be ported to an FPGA. I wonder if 4 megs are enough. I am contemplating designing a board with Cellular RAM, which is a good compromise between memory capacity, performance, price, and firmware complexity. An FPGA based board with 32 megabyte of Cellular RAM is quite feasible. Such a board can certainly run System-3. 


> I have read with more than passing interest regarding comments on implementing Oberon 2 for RISC5 targets.

More information about the Oberon mailing list