[Oberon] Other CONST.

Chris Burrows chris at cfbsoftware.com
Mon Jan 7 12:30:23 CET 2019

> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> peter at easthope.ca
> Sent: Monday, 7 January 2019 11:38 AM
> To: oberon at lists.inf.ethz.ch
> Subject: [Oberon] Re (2): Other CONST.
> Incidentally, during the last year or more, some or much discussion
> has involved the 1 MB memory of the FPGA machine.  Peter has this
> remark at the top of risc.c.
> // The FPGA uses a 20-bit address bus and thus ignores the top 12
> bits.

AFAIK that information is obsolete. The RISC5 address bus width, as defined
in the Verilog source, was increased from 20 to 24 bits in Sep 2015. I have
had the 2 MB version of the Pepino Spartan-6 LX25 development board for some
time now but haven't yet found any use for the additional 1 MB ;-)


Chris Burrows
CFB Software

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