[Oberon] RAM capacity for Oberon

Paul Reed paulreed at paddedcell.com
Wed Jan 9 23:47:41 CET 2019

Hi Wojtek,

> Mem type  capacity  $/MB
> ASRAM   1 or MB    $12
> ZBT     2 or 4 MB    $9
> CRAM    16      $0.33
> HRAM    16      $0.40
> SDRAM   32 or 64   $0.18
> LPDDR   128      $0.06
> DDR3L   256    $0.02

It's great to keep chipping away at this problem (no pun intended!) but as
I noted soon after the discussion came around to expanding the RISC5
memory possibilities, unless I've missed something there's not much to
match 10nS asynchronous static RAM in terms of speed or simplicity, hence
the (I make it) ~$5 per megabyte, for one megabyte (IS61WV25616BLL-10 x 2
at Digi-Key) seems pretty good value.

In particular, all the other RAM styles seem to be a LOT slower for random
access, and as Prof. Wirth notes in "The Design of a RISC Architecture and
its Implementation with an FPGA" [1], less predictable.

And the main point of Project Oberon is to keep the design simple enough
to be understood in its entirety.  Of course, $5 just for the RAM is a lot
of money when it also equals one Raspberry Pi Zero.  So if you need a lot
more memory and a wide range of features and compatibilities, why not go
for that, and accept the attendant complexity (of hardware and software -
Linux has this very well-covered).  You can get FPGA add-on boards for the

That's not to say that DDR SDRAM, for example, can't be used as a large
data store in a simpler system, I think that's already been suggested. 
Prof. Wirth did this with the SRAM on the Spartan 3 board with RISC1
before going to the full Von-Neumann design with RISC3.  With careful
design (always a theme with Prof. Wirth!), 1MB of static RAM for the
program and heap may be just fine.


[1] https://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC.pdf

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