[Oberon] RAM capacity for Oberon

Paul Reed paulreed at paddedcell.com
Thu Jan 10 19:06:15 CET 2019

Hi Wojtek,

> ...ZBT is both faster and more predictable than ASRAM

I have to disagree, there's nothing unpredictable about asynchronous
static RAM in this context, it's about as predictable as it gets.

What you are calling ZBT (and ISSI more clumsily calls "Pipeline 'No Wait'
State Bus Synchronous SRAM" [with no hyphen to help!]) is as predictable,
but with more cycle latency, so as you say, you need to skip clocks when
doing random access.

The datasheet rather disingenuously quotes a "clock access time" (again no
hyphen!) of 2.6ns or 3ns for the 250MHz or 200MHz part respectively but
the cycle time, it seems to me, is what counts, which is 5ns for the
200MHz part in your example, so with skipping for random addresses it's
10ns.  And that's theoretical - surely a lot of care needs to be taken
with a 200MHz clock.

And if you're being theoretical you can get a lot closer to 100MHz with
10ns asynchronous RAM too, 25MHz is not the limit, nowhere near.  It just
so happens that the RISC5 has a cycle time of 25MHz for other reasons,
pointed out very well in the past by Magnus.

However, of course with synchronous RAM you might be able to use the
skipped cycles for video access (if this were important) so I agree that
in that case it's technically a little faster.  In that one case, if you
can get it to work.

But we do agree it's a lot more complicated than asynchronous SRAM.  And
we also agree that the other RAM choices get much more complicated still. 
And certainly less predictable.

Also, what about availability?  There are at least three different
manufacturers for the 256K x 16 10ns asynchronous SRAM part, all with the
same pinout and spec.  Digilent already had to discontinue one perfectly
good FPGA board because the RAM part was discontinued.  THAT was sobering!

Finally, the pricing - I see now what the misunderstanding was, you chose
512K x 16 asynchronous SRAM to get $13 per megabyte, for two megabytes. 
If you choose 256K x 16 SRAMs as used in the RISC5 reference design and
several other boards, it's about $5 per megabyte as I said.  So you've
really got to want your two megabytes in two chips to pay your $26!  :)

> I chose the ZBT for my RiskFive project, and I am now watching with
> amazement how students cannot make sense of it.
> Part of the student's problem is the RISC5 Verilog code, which is
> extremely terse and unforgiving for understanding.

My experience is that Prof. Wirth's Verilog code is a lot more
understandable than most supposedly serious Verilog code out there
(serious meaning implements more than an 8-bit counter or whatever) and a
breath of fresh air compared with commercial reference designs I've had to
deal with, unbelievably.

Furthermore, you have a complete description of the evolution of the
design, and also the Lola implementations, which give another angle.  All
this should be extremely helpful, and so I really don't think that's the
most difficult part of the task.  What you've asked the students to do is
just really hard, you shouldn't be amazed.

I actually think at the high level, for what you are trying to do, it may
be better to use something like RISC-V, which is built rather well for
such purposes, rather than Prof. Wirth's RISC5, which certainly is not.

Nevertheless, please feel free to get the students to mail the list.  I'll
try to help where I can and some others might be able to too.  The actual
problems they are having are probably of interest to some in the first
instance, and if it gets too specific we can always take it offline.


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