[Oberon] FPGA - JTAG programming

Skulski, Wojciech skulski at pas.rochester.edu
Mon Jan 21 22:52:08 CET 2019

From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Tomas Kral [thomas.kral at email.cz]
Sent: Monday, January 21, 2019 4:24 PM
To: Oberon at lists.inf.ethz.ch
Subject: [Oberon] FPGA - JTAG programming


I often change between different FPGA bit files, doing soft
reprogramming the chip. Just wondering, how many reprogrammings the
Xiling chip can take? Is there a physical limit?

Tomas Kral <thomas.kral at email.cz>
Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems

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