[Oberon] Resend: Re: Risc-5 Instructions statistics

Walter Gallegos waltergallegos at vera.com.uy
Sun Feb 17 14:33:47 CET 2019


Yes for me the focus is the special hardware not the micro-controller. 
Let me try to explain for what I insist at point. In advance, I do not 
try to "evangelize" anyone.

Unfortunately or fortunately, only a point of view ;), I come from 
hardware, from FPGA hardware even worst from industrial FPGA hardware, 
game rules are different.

To use a 28 USD chip I need justify that this chip provide the best 
solution. A basic rule in industry is : a project use FPGA because is 
the only practical solution if not use a micro-controller.

In this context chose a bigger component adding 6.44 USD to the costs 
when an external 50MHz ARM cost around 3.5 USD could be hard to justify. 
Beside the cost of a chip is the development cost that in case of ARM is 
significantly lower because it is a better know component than an FPGA.

Combined this cost with Paul numbers I could conclude that in the case 
of DSP blocks for multiplication add 6.44 USD to the cost of each unit 
optimize only 0.15% of the software. A conclusion drawn from the hairs I 
agree but illustrate the type of analysis that we need do.

I insist because I would like to see a growing community but for that it 
has to fit into the industry and play by it rules.



El 17/2/19 a las 01:17, Skulski, Wojciech escribió:
> Walter:
> Walter Gallegos [waltergallegos at vera.com.uy] said:
>> Implementing a general propose microprocessor system alone
>> in FPGA is impractical beyond the research or ASIC prototypes.
> I agree, but... The motivation for RISC5 was that Oberon System software was available. The traditional rules of computer design have been turned upside down. Traditionally, the CPU is designed first, and compilers and other software are then developed to support the CPU. Here it was just the opposite. The operating system existed. The CPU was then designed to run the software, not the other way around. This course of actions seems pretty unique to me.
>> For industrial applications the microprocessor must coexist
>> with some special hardware that justifies the use of FPGA.
> A very good point. But it can be turned upside down too. The "special hardware" can be termed a "coprocessor" for the microprocessor. It depends what is more important to you. The Oberon programmers will probably put the RISC5 and its software in the foreground. They will probably say that the "special hardware" is bunch of registers plus some obscure logic delivering the content to these registers. Your point of view may be the opposite. To you, the "special hardware" is the focus, while the CPU is a necessary devil to set it up and to monitor its operation.
>> In this environment, wasting DSP blocks
>> could be a not recommended technique.
> If you say "wasting", it means that you need them for something else. Then you are presumably building a coprocessor ("special hardware") where you need these blocks. This in turn implies that you are designing in a resource starved environment and you need to compromise either the CPU or the "special hardware" because there are not enough DSP blocks for both. If so, then I would ask: why not choose a slightly larger FPGA with more DSP blocks?
> Let me give an example of a particular Artix FPGA and the next higher Artix in the same FT256 footprint. I took the price from DigiKey.
> XC7A15T-1FTG256C $27.93  45 DSP blocks
> XC7A35T-1FTG256C $34.37  90 DSP blocks
> Thanks,
> Wojtek
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
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