[Oberon] [Oberon...] Risc-5 Instructions statistics

[Walter Gallegos]

Hi Paul

Useful information.

Confirms experimental trends from my applications, example has no sense 
waste DSP48 blocks implementing a 32 X 32 bits multiplication.

Thank you.

Walter

El 15/2/19 a las 15:20, Paul Reed escribió:
> Hi Walter, Joerg,
>
>> Someone have or know where to find statistics of use of RISC-5
>> instructions in Oberon-07 programs ?
>> I only quickly analyzed the four compiler modules. Here the distribution:
>>   Format 0     2%  register instructions, register
>> Format 1   26%  register instructions, immediate
>> Format 2   49%  memory instructions (LDR/STR)  (<-- cache would really be
>> great!!) Format 3   23%  branch instructions
> I added some instrumentation to my own RISC emulator a while back.
>
> For a complete recompile of my system, the instructions executed are as
> follows:
>
> total instructions executed 235144906
>
> Arith (F0 and F1) 56377763 (23%)
>    ( nofOp[0]   2888035 (5%)  nofOp[1]   1635477 (2%)  nofOp[2] 492673 (0%)
> nofOp[3] 191597 (0%)
>      nofOp[4]    640692 (1%)  nofOp[5]      7423 (0%)  nofOp[6]  16308 (0%)
> nofOp[7]  17930 (0%)
>      nofOp[8] 26864507 (47%)  nofOp[9] 23219248 (41%) nofOp[10] 388938 (0%)
> nofOp[11] 12964 (0%)
>     nofOp[12]       996 (0%) nofOp[13]         0 (0%) nofOp[14]    880 (0%)
> nofOp[15]    95 (0%) )
> nofLdr 92107302 (39%) nofLdb 9123136 (3%)
> nofStr 26208017 (11%) nofStb 2858250 (1%)
> nofBrt 20911510 (8%) nofBrnt 27558928 (11%)  (branches taken and not taken)
>
> Of course, YMMV, but I hope that helps,
> Paul
>
>
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
>