[Oberon] Alternatives for cases.
andreas_pirklbauer at yahoo.com
Sat Mar 9 06:31:15 CET 2019
> > 2) If so, do you have data for a CASE statement that
> > does not use the B, cond PC, [Rn] instruction?
> Time is 44 ms. i.e. about a 5% improvement. I wouldn't expect any more than that because
> the 50% gain in CASE selection overhead is swamped by the other code that is executing
> for each selection. i.e. the average gain is n + 9 / n + 6 where n is the average of the total
> number of instructions executed for each branch.
> Data (bytes) Code (bytes) Time (ms)
> CASE OLD 8 1072 44
Oh, that’s interesting… this gives me a little bit more comfort (“I’m not that far
behind after all”) for my own implementation of the numeric CASE statement
which does NOT use the modified Branch Conditional instruction.
> While numeric CASE is not implemented in the official RISC compiler it is not
> necessary for the instruction to be included in the official RISC spec.
Of course not. I have implemented the CASE without it, with the stated difference.
> If numeric CASE is eventually implemented I would be very surprised
> if a similar instruction or something even more suitable (e.g. the CASEi
> instruction of the NS32000 instruction set) did not appear at the same time.
On the other hand: Doesn't the above data (“only” a 5% improvement) suggest
that such an enhanced Branch Condition instruction may not be justified after all?
So my hunch is that *if” the numeric CASE is ever added back, it would come
with something similar to CASEi of the NS32K which was fast indeed (*)
But I have a sneaking suspicion that there may have been other (than
performance-related) reasons for not implementing the numeric CASE
statement in the official FPGA Oberon release.
(*) but if I remember correctly several NS instructions got slower (!)
over time in later versions of the NS processor - because it got internally
re-architected using microcode, following the general industry trend that
started around that time of implementing only frequent, simple instructions
directly with hardware, while implementing more complex instructions
using internal microcode (CISC to RISC).
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