[Oberon] Oberon on ULX3S explanation

D EMARD vordah at gmail.com
Mon Nov 11 22:58:35 CET 2019

ULX3S is cool board designed by EMARD aka me :)


There should be currently a small of batch of ULX3S production at watterott
I don't know are they already sold out but it's not bad to ask


or maybe Goran can help also: goran.mahovlic at gmail.com

Apart from that ULX3S is open hardware and anyone can theoretically ask
any PCBA manufacturer, some did it successfully


to make it out of source here


or here


On 11/11/19, Paul Reed <paulreed at paddedcell.com> wrote:
> Dear Mr. Emard,
>> We have on ULX3S FPGA tried oberon and it works nice
>> on 32MB SDRAM at oberon's simple risc CPU, clock 25MHz.
> That sounds great!  As most people do not have a ULX3S, might you be
> able to give a brief technical explanation, to describe broadly how it
> was done, which might for example be of help to people who already have
> other FPGA boards which have synchronous DRAM?  It might also help our
> discussions.
> Thanks,
> Paul Reed
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon

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