[Oberon] SDRAM performance

Skulski, Wojciech skulski at pas.rochester.edu
Fri Nov 15 22:16:27 CET 2019

> as hypeRAM has some logic solved on-chip like internal refresh,
> driver core should be be a bit simpler than SDRAM but still would be
> a non-trivial core.

In one of my previous e-mail I provided URLs for three different HyperRAM firmware controllers. At least one looks fairly reasonable.

>it would need additional time critical part: clock domain crossing
>logic operating between 333 MHz RAM and say 50 MHz CPU/video. 

FIFO of course. BTW, HyperRAM operates at up 166 MHz DDR, rather than 333 MHz. 

>From my experience clocking any complex design above 100 MHz in
>FPGA is lottery. Very small and simple cores can stand 200 MHz.
>For above 300 MHz, just a simple logic - few regs, counters that's all.

In our flagship digitizer we are receiving ADC data at 800 MHz. We also interfaced the GbE PHY using the SGMII running at 1.25 GHz. It was not a lottery. It was a careful design. But it was also lots of work. There is no doubt here. 

I feel quite confident that HyperRAM is within reach. I feel that firmware is a bigger problem than hardware. Both the Cellular RAM and HyperRAM take out the complex controller firmware from the SoC and move it to within the RAM chip. The remaining firmware is much less complex. Please have a look at the first HyperRAM controller from my earlier e-mail. It looks good to me and it is well documented.


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