[Oberon] FPGA RISC memory interfacing

Skulski, Wojciech skulski at pas.rochester.edu
Tue Dec 24 01:05:13 CET 2019


>It could be something wrong with that board.
>You can send it back for a replacement board if this is a recurring problem.

After a few hours the System is still running on Pepino. Sierpinski.Draw looks good. Hilbert.Draw is outputting pieces all over the screen. I will have to look a bit deeper because the SD passed through many hands. I doubt anyone changed the SW, but who knows. I will order the new Pepino anyway.

I am puzzled with your comment on github "Backing out the changes to make is synchronous". Does it mean that you tried to add proper clocking to the Verlilog design and you resigned from doing so? I now tend to believe that all RISC5 files need to be made synchronous. Any comment?

Thank you,

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