[Oberon] QEMU target implementation for Oberon RISC architecture

Luca Boasso luke.boasso at gmail.com
Sat Dec 28 03:20:13 CET 2019

Thank you very much for sharing your work. It looks promising so far,

On Fri, Dec 27, 2019, 17:37 Charles Perkins <chuck at kuracali.com> wrote:

> This is to let you all know about a fork of QEMU (a very fast emulator
> with lots of features) introducing the Oberon RISC architecture.
> https://github.com/io-core/qemu-risc6
> It is unfinished and I probably should have waited to announce it but the
> new year starts soon and I just want to share some pretty (to me) pictures.
> As it says in the readme on the github page, the target is named risc6 to
> avoid confusion with the already existing riscv target in qemu and because
> in one communication (An Update of the RISC5 Implementation
> <https://inf.ethz.ch/personal/wirth/ProjectOberon/RISC5.Update.pdf>)
> Professor Wirth defines module RISC6 to introduce interrupts into the
> architecture.
> I intend to update the readme with build instructions and binaries that
> can be simply downloaded, etc.
> Happy Hacking,
> Chuck
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
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