[Oberon] QEMU target implementation for Oberon RISC architecture
paulreed at paddedcell.com
Mon Dec 30 09:55:54 CET 2019
> ...the target is named risc6
> to avoid confusion with the already existing riscv target in qemu and
> because in one communication (An Update of the RISC5 Implementation
> ) Professor Wirth defines module RISC6 to introduce interrupts into
> the architecture.
Sorry I think that's a mis-print since it's the only occurrence, I'm
pretty sure the intention was to keep it as RISC5. Apologies for any
As it happens most of the stuff for interrupts was there originally
anyway before the update, especially in the compiler. The RISC5 source
on Prof. Wirth's site definitely contains the interrupt code now.
There's also a RISC5a version, without interrupts and without
More information about the Oberon