[Oberon] QEMU target implementation for Oberon RISC architecture

[Andreas Pirklbauer]

    > cpu := SYSTEM.H(2019) MOD 80H;
    > IF cpu = 53H THEN       (* RISC5: with interrupts + floating-point, 31.8.2018 *)
    > ELSIF cpu = 54H THEN (* RISC5a: no interrupts, no floating-point, 1.9.2018*)
    > ELSIF cpu = A0H THEN (* RISC0, 26.12.2013 *)
    > END ;

BTW, my system (in an emulator) returns cpu = 50H, i.e. none of the above values.