[Oberon] Interfacing with Foreign Systems
joerg.straube at iaeth.ch
Sat May 2 16:38:43 CEST 2020
The Oberon OS as it exists for RISC5 today is in my point too limited to build a good starting point for a native OS on any commercial HW board.
Just one example: the SW architecture for HW drivers (if you can speak of an architecture at all) is too slim and too static. There is Kernel (driving timer, clock and disk), Input (driving mouse and keyboard) and Display (driving the screen)
The existing APIs do not allow to change the keyboard layout, nor to change the resolution.
At least a FAT16/LFN filesystem implementation, a TCP/IP API and an USB API should be part of a „modern“ OS. As these protocols are complex beasts, I could imagine that coding those will need quite some memory. Perhaps too big for the 1MB my FPGA board currently has.
But indeed running ProjectOberon natively on a RasPi would be nice😊.
>> Am 02.05.2020 um 00:17 schrieb Guy T. <turgu666 at gmail.com>:
> From your answer, I understand that you would prefer a simple solution in the same realm as the FPGA based NW Risc5 design. This is certainly an aspect that need to be considered.
> The reality today is that I don’t see any ready-made processor chip available that would be simple enough to be a contender to a simpler FPGA design, unless you look at old technologies no longer available elsewhere than on eBay. The ESP32 I’m working on cost me around $4 CDN each and it comes with around 1450 pages of describing both the CPU architecture (around 660 pages) and the 20+ interfaces in a technical reference manual (around 680 pages), and this doesn’t take into account the ESP-IDF framework.
> The NW design is very interesting and very useful for computer science education. But the reality right now is the difficulty to get access to a ready made board that would survive for a reasonable amount of time in term of availability, unless an open design is made available and simple enough for a guy like me (I’m a hobbyist in electronics) or a student that would be able to build one in his basement. The last board have seen is the ulx32 (https://www.crowdsupply.com/radiona/ulx3s). Very interesting, but will it survive? (it is too complex to be built at home) I hope so, unless other alternatives appear.
> Maybe the solution is to follow two tracks: An FPGA based solution and a commercial board based solution (read: Raspberry Pi and/or BlackBerry like boards). Nothing is perfect here.
> Again, it's all depend on the orientations that the community wants to take.
> Me, I don’t really care to what orientation will be taken. For now, I’m using the risc5 emulator on my laptop and have fun in building the compiler for the ESP32. IOT development is my current spin. I would be more serious in developing stuff with the Oberon OS if I can get an interesting platform to run it.
> >> What about the RISC-V processor. It is supposed to be an open architecture. Is there anybody with some knowledge about it?
> >There are RISC-V experts in this forum. I can only offer a quote and an opinion:
> >Quote: RISC-V is featuring "a cornucopia of simulators, applications in the object tool chain, debuggers, C compilers and libraries (also compilers and runtimes for other languages), boot loaders and monitors, kernels and operating systems, and integrated development environments (IDEs) .
> >1. Max Maxfield, Introducing RISC-V and RISC-V Tools, February 14, 2019,
> >My opinion: Tools of this complexity can hardly fulfill their open source promise outside the realm of hardcore developers.
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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