[Oberon] EFLAGS & etc.

Jörg joerg.straube at iaeth.ch
Mon May 4 09:31:28 CEST 2020

Hi Lyall

I had a quick look. I don't know exactly but I have an idea:
In Native Oberon HW interrupts are handled as follows:
1) HW generates an interrupt and the Intel CPU reacts
2) the Oberon OS gets the interrupt and dispatches it to your interrupt handler
3) your interrupt routine does the thing you want it to be done to handle the interrupt and returns normally to the Oberon OS.
4) The Oberon OS does some clean up and returns from the interrupt

The shown stack layout is the stack layout as seen by your interrupt handler, so 1) after the HW interrupt occurred and 2) after the OS dispatched it to you.

The values marked with '' (48..56) are pushed on the stack by the CPU before the Oberon OS interrupt handler is called. All other values (0..44) are pushed on the stack by the OS before your handler is called. They represent the exact state of all registers at the time the interrupt occurred.
To call your handler, the OS needs to overwrite the stack pointer ESP, the instruction pointer EIP and the base pointer EBP. These three vital registers are marked with ' to tell you, that in your interrupt handler the ESP, EIP and EBP are NOT as they were when the interrupt occurred. In case your interrupt handler needs the originals, you can find them on the stack.


Am 03.05.20, 18:53 schrieb "oberon-bounces at lists.inf.ethz.ch im Auftrag von peter at easthope.ca" <oberon-bounces at lists.inf.ethz.ch im Auftrag von peter at easthope.ca>:

    Hello again,
    Will someone please glance at the bottom of this page.
    What is the signifiicance of the apostrophes as in EFLAGS'' and EIP'?
    I've checked a few pages including this.
    Nothing helpful.
    Thanks,                          ... Lyall E.
    Tel: +1 604 670 0140            Bcc: peter at easthope. ca
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