[Oberon] Re (2): Hardware; was: Development boards
skulski at pas.rochester.edu
Mon May 4 15:47:33 CEST 2020
> I'm willing to hypothesize a convergence for
> the FPGA. Greater complexity producing a longer convergence time. A
> range of capacities rather than only two. I might be absolutely wrong
> but technologies do tend to converge.
No. Other than the HDL the standardization does not exist and it never will. "Never" means "till we both retire".
When I wrote "tools" I meant languages. The "tools" can also mean a particular installation like ISE or Vivado. There is little standardization even within one vendor when it comes to those tools. They both support Verilog, VHDL, and perhaps EDIF. But the rest is scattered from the North Pole to the South Pole. Like for example timing constraint specification. There is a particular text format named User Constraint File (UCF) under ISE. It is pretty straightforward though ugly. Do you think that the Xilinx ISE UCF file can be read under Xilinx Vivado? My FPGA guys tell me it cannot. The same thing, two different ways. Note that both ISE and Vivado are from Xilinx.
I am not surprised that besides HDL not much is common among Xilinx, Lattice, and Altera. Anything which is device-specific is coded different way. Even within one vendor it can change from tool to tool. So when I said "kind of easily" I really meant "kind of".
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