[Oberon] Unlimited Oberon System for any board

[Jörg]

Could be doable. But the ISA doesn't bring much, if you don't have a compiler.
(Cross-)compiler first, then ISA.
Jörg

Am 08.05.20, 16:18 schrieb "Oberon im Auftrag von Guy T." <oberon-bounces at lists.inf.ethz.ch im Auftrag von turgu666 at gmail.com>:

    What about using RISC-V ISA on FPGA, allowing for “some kind of” easy path between RISC-V chips and FPGA made systems?
    
    Guy
    
    > On May 8, 2020, at 9:58 AM, Jörg <joerg.straube at iaeth.ch> wrote:
    > 
    > Hi Guy
    > Thx for the link. As I can see, it takes (complex) S3 as OS. And it's Oberon-2 not Oberon-07. As you said: it's a start.
    > I started looking into the RISC-V ISA and thought, perhaps it's possible to find an easy mapping to the RISC5 ISA...
    > At first sight, 1:1 is not totally possible as the immediates of RISC-V are somewhat shorter...
    > Jörg
    > 
    > Am 08.05.20, 15:45 schrieb "Oberon im Auftrag von Guy T." <oberon-bounces at lists.inf.ethz.ch im Auftrag von turgu666 at gmail.com>:
    > 
    >    There is already a compiler to start with for RISC-V:
    > 
    >    http://oberon.wikidot.com/oberon-linux-revival-olr
    > 
    >    Guy
    > 
    >> On May 8, 2020, at 9:34 AM, Jörg <joerg.straube at iaeth.ch> wrote:
    >> 
    >> Paul
    >> Are you proposing to start writing an Oberon compiler for RISC-V?
    >> Jörg
    >> 
    >> Am 08.05.20, 14:28 schrieb "Oberon im Auftrag von Paul Reed" <oberon-bounces at lists.inf.ethz.ch im Auftrag von paulreed at paddedcell.com>:
    >> 
    >>   Hi Andreas,
    >> 
    >>> ...For example, RISC-V is the first “simple enough” system in 
    >>> decades...
    >> 
    >>   That may be true, for some value of "simple enough", but it is not 
    >>   simple.
    >> 
    >>   So you have hit the nail on the head: to those who wish to turn RISC5 
    >>   into RISC-V, I plead: use RISC-V.
    >> 
    >>   Cheers,
    >>   Paul
    >>   --
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