[Oberon] What boot LEDs mean, point me to some docs
joerg.straube at iaeth.ch
Sun Oct 25 06:43:13 CET 2020
You‘re right. These LED states are handled by code in ROM:
D7 = 80H = Init SPI
D7 + D0 = 81H = load inner core from RS232
D7 + D1 = 82H = load inner core from CF
D7 + D2 = 84H = transfer execution to inner core (RAM address 0)
> Am 24.10.2020 um 22:56 schrieb Michael Schierl <schierlm at gmx.de>:
> Hello Jörg,
> D7+D2 is 84H, not 82H.
> (D0=1H, D1=2H, D2=4H, D3=8H, D4=10H, D5=20H, D6=40H, D7=80H)
> If reading from RAM or writing to RAM were totally broken, it would not
> get that far.
> One possible reason (just a guess) would be if RAM reading as data
> works, but reading as code would not. Since at that point a RAM
> instruction is executed for the first time (before it was all in ROM).
> But as for most memory problems, it could be many other things as well.
>> Am 24.10.2020 um 16:49 schrieb Jörg:
>> As it’s stuck on 82H it could be that the boot loader could not not load the oberon core from CF to memory.
>> If the boot loader finished loading the oberon core, but the core hangs, leds would stick on 80H.
>> If something is wrong with the memory, the behaviour is difficult to predict. When I added SDRAM and did something wrong in the beginning, the inner core created „strange“ C2H sometimes C4H traps.
>> Br, Jörg
>>>> Am 24.10.2020 um 16:22 schrieb Michael Schierl <schierlm at gmx.de>:
>>>> Am 24.10.2020 um 15:50 schrieb D EMARD:
>>>> A collegue is rying to make cleaner rework of SDRAM and cache for
>>>> oberon at ulx3s board
>>>> Old code which works has this boot LED sequence (or bits):
>>>> D7+D1, D7+D2, D5 ... then video, mouse and kbd work
>>>> New code under development boots
>>>> D7+D1, D7+2 and stays there
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