[Oberon] [EXT] Project Oberon, RISC-V Edition
skulski at pas.rochester.edu
Mon Dec 7 04:15:33 CET 2020
> And there is always the FPGA route to consider.
Speaking of RISC-V and FPGA, someone (Peter Matthias I think) once said that Artix-7 100T is sufficient to run a soft version of RISC-V. I also recall seeing such statements somewhere on the RISC-V sites. If this is true, and if you are happy with the soft RISC-V, then you can order RiskFive with Artix 100-T from me. You will need to pay for the production run, but this is peanuts. A couple thousand or so. Then you will have your FPGA board and the production files. If the board goes under at my end, then you can still repeat the production runs basically forever.
Other possible boards include Arty-7 with Artix-7 100T from Digilent. It has more memory, but it is DDR3, so you will need a much more complex firmware. But you need to do it once. Also, you can perhaps find an EE intern or two who can interface DDR3 for you.
The advantage of RiskFive is that it has a static RAM which is not that big a deal like DDR3 is. I just posted a preliminary firmware for RiskFive. The disadvantage is that RiskFive has only 4 MB of that RAM.
Nexys A7 with Artix-7 A100T from Digilent is inexpensive and it has 128 MiB of DDR2, which is less demanding than DDR3.
Going up in price, you can order a Kintex-7 from Digilent and then you can run a larger RISC-V soft core. Genesys 2 with Kintex-7 is only $1k, and the FPGA is pretty hefty.
So there are ways out, if you decide that you do not need to do everything yourself. If you insist on DIY, and you want it cheap, and well supported, and stable, and forever... then it can be tough.
More information about the Oberon