[Oberon] [EXT] Re: Project Oberon, RISC-V Edition

Skulski, Wojciech skulski at pas.rochester.edu
Tue Dec 8 17:26:36 CET 2020


>The LPDDR of the Pipistrello works nicely.

I know. It is great. You need the cache, though. I know you have implemented it.

If you look at the table below, higher clock speed brings more complexity. DDR3 requires dedicated phase calibrations of the received signals. Tuning the signals is performed in the memory controller. This logic uses lots of resources. The other memories, which are running slower, have wider timing margins and do not need that much tuning and calibration. From this point of view it pays to stay with the older technologies. 

I mentioned DDR3 because Andreas asked about the boards. OK, there are boards out there. Arty is inexpensive, so it is a good candidate. But they put DDR3 on that board. So one has to ask how to possibly use it. You can read the discussion on http://opencores.org/project,wbddr3 by Dan Gisselquist. It is a horror story. The numbers in the table are saying the same.

> DDR3 SDRAM(2) 14,016   67%
> DDR2 SDRAM(2)  9,267   45%
> LPDDR2 SDRAM   3,952   19%

On my next board I will either provide PSRAM or HyperRAM. The refresh is then moved from the FPGA to the memory chip itself. PSRAM can emulate ASRAM, so one can use the present Oberon Verilog with little change. It is also possible to use PSRAM in the synchronous mode to boost the performance. All this without ever worrying about the refresh controller.


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