[Oberon] Fixup documentation; was: Documentation;

[Hellwig Geisse]

Peter,

On Do, 2020-12-17 at 07:10 -0800, peter at easthope.ca wrote:
> 
> > In the risk architecture you find the following hint: 
> > „If v = 1, the link address PC+1 is deposited in register R15.  ...
> Encoded in Verilog.(?)
> 

yes, as follows:

Register writes are executed in the statement
    always @ (posedge clk) begin
      ...
      R[ira0] <= regwr ? regmux : A;
      ...
    end

The register number "ira0" is 15 in case of a BR
(all branch instructions, including calls):
    assign BR = p & q;
    assign ira0 = BR ? 4'd15 : ira;

The condition "regwr" is true for calls that are
actually executed ("BR & cond & v"):
    assign regwr = ~p & ~stall | (LDR & ~stall1) | (BR & cond & v);

In this case, "regmux" is PC+1 ("nxpc"), shifted
left by 2 bits (because the remembered address in
R15 - the "return address" - is a byte address,
in contrast to the word address of the PC):
    assign nxpc = PC + 22'h1;
    assign regmux = LDR ? {inbusH, inbusL} : (BR & v) ? {8'b0, nxpc, 2'b0} : aluRes;
The curly braces "{...}" denote concatenation of
bit vectors in Verilog.

Hope that helps - sorry for the rather brief explanation.

Hellwig