[Oberon] Project Oberon 2013 on RISC-V

Charles Perkins chuck at kuracali.com
Sun Dec 20 18:13:18 CET 2020


On Sun, Dec 20, 2020 at 8:54 AM Rikke Solbjørg <rikke.solbjorg at gmail.com>

> Hi,
> I saw your recent discussion on running Project Oberon on RISC-V. I've
> been working on a RISC-V port for the last few months, which might be
> interesting to you. A port of Project Oberon to RISC-V (i.e. a RV32IM
> compiler and a port of the rest of the system), as well as an emulator that
> can run it, can be found in these repositories:
> https://github.com/solbjorg/oberon-riscv
> https://github.com/solbjorg/oberon-riscv-emu
> If you just want to try it, there's a disk image included with the
> emulator.
> To my knowledge, this RISC-V port is more complete than others that I have
> found: the compiler can compile the Oberon system as well as itself, and
> the system runs well in the emulator. It lacks support for REALs and
> interrupts at the moment, but most programs are able to run without them.
> The port is built on top of several other Oberon-related projects, which
> I've credited in oberon-riscv's readme.
> I'm planning to make it run on an FPGA in the future too, although that
> will have to come after the holidays.
> Kind regards,
> Rikke
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
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